Applications of space-charge-limited conduction induced current increase in nitride-oxide dielectric capacitors: voltage regulator for power supply system and others

ABSTRACT

A capacitor structure having a re-oxide layer on a nitride layer, wherein an interface between the nitride layer and the re-oxide layer includes electron traps. Characteristics of the carrier traps control a voltage output of the device. The thickness of the nitride layer and the re-oxide layer also control the voltage output. The nitride layer and a re-oxide layer form a dielectric capacitor. The dielectric capacitor undergoes a trap filled limit voltage, wherein a consistent voltage is output for a plurality of currents.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to the applications ofspace-charge-limited conduction (SCLC) induced current increase innitride-oxide dielectric capacitors. One major application of theinvention is with a voltage regulator and more particularly to anitride-oxide dielectric capacitor voltage regulator. This invention isalso applicable to other applications such as DRAM process controls(node dielectric thickness, defect, film uniformity, etc.), voltagesensors, space-charge-limited dielectric amplifiers, and SCLC memorydevices.

2. Description of the Related Art

Voltage regulators are important components in power supply circuits andare used to maintain constant output voltage regardless of minorvariations in load current or input voltage. For example, commonly usedvoltage regulators range from simple Zener regulators to relativelycomplicated voltage-regulating circuits. Tremendous amounts of wastepower and relatively high temperature sensitivity make simpletwo-terminal Zener diode regulators impractical for on-chip power supplycircuits.

Integrated voltage-regulating circuits can achieve much better powerperformance than Zener diodes; however, they employ many devices such asMOSFETs, capacitors, diodes, and resistors. Thus, they are structurallymore complicated and physically consume larger die space than simplediodes or capacitor regulators. Although voltage regulators could beimplemented off-chip or on-package to save die space, thisimplementation is not as effective and easy to use as on-chip very largescale integrated circuits (VLSIs).

The continued scaling down of DRAM cell sizes requires a thinner, higherquality, and more reliable storage node dielectric to compensate fordecreased surface area and to reduce defect density. Recent trends haveshown that the nitride-oxide stacked dielectric thin film becomes anattractive choice for the storage capacitor of large DRAM chips.However, the individual thickness of each layer (nitride and oxide) andthe information about the traps inside this material system are hard tomeasure and control. Conventionally, a capacitance-voltage (C-V) methodis used to obtain the electrical thickness and trap concentration forthe device. However, C-V measurements can only measure the totalthickness (the effective thickness) of the stack. C-V data analysis isdifficult due to impacts from quantum-mechanical effects, gate leakagecurrent, and series resistance effects caused by aggressive scaling ofthe dielectric thickness. Furthermore, the C-V method alone cannotdetermine the energy level of the traps. TEM is another methodconventionally used to determine physical thickness of stackedstructure. However, it is destructive, costly, localized, and tedious.It cannot be used for determining uniformity across the wafer or used asa routine in-line monitor.

BRIEF SUMMARY OF THE INVENTION

The invention provides a nitride-oxide stacked structure that producesan abrupt current increase at the voltage VTFL (trap filled limitvoltage) prior to dielectric breakdown. Both planar and deep trench typedevices could be fabricated by using this structure. Two things happenwhen the VTFL is reached, first, the capacitor current increasesdrastically. Secondly, the applied voltage across the capacitor remainsrelatively constant over a wide range of device current values. Numerousapplications, such as voltage regulator, voltage sensor, DRAM/eDRAMprocess control, and SCLC memory device, find benefit with thisinventive structure.

In order to attain the object(s) suggested above, there is provided,according to one aspect of the invention, a structure which has anitride layer, a reoxidized nitride (re-oxide) layer on a nitride layer,and input and output connections. There are carrier traps inside thenitride layer and at the interface between the nitride and re-oxidelayer. Characteristics of the carrier traps control a voltage output ofthe device. The thickness of the nitride layer and the re-oxide layeralso control the voltage output. The nitride layer and a re-oxide layerform a dielectric capacitor. The dielectric capacitor undergoes a trapfilled limit voltage, wherein a constant voltage is output for aplurality of currents. The trap filled limit voltage events can occur atdifferent current levels, such that the invention produces a multi-valuevoltage regulator in one embodiment.

The power consumption of the invention's two-terminal N-O capacitorbased voltage regulator is much less than Zener diodes based voltageregulator since it is operated below the dielectric breakdown voltage.The leakage current tunneling through amorphous N-O film is much lessthan the leakage current traveling through Si after breakdown of a Zenerdiode.

The present invention's N-O trench type voltage regulator has extremelyhigh density (deep trench approach) design and is the best choice forspace saving. On-chip voltage regulation with mass integration becomespossible by using the deep trench N-O capacitor as a inventive voltageregulator. This approach is also easily integrated and has low cost.

The invention is also useful with dynamic random access memory (DRAM)process control. Details of SCLC conduction parameters depend on thethickness and temperature. VTFL voltages are shown below to beproportional to the square of the film thickness. Since the re-oxidethickness is kept constant for all of the films, the variation of VTFLdepends on nitride thickness only. There is no electrical methodconventionally available to detect nitride thickness and re-oxidethickness separately for N-O stacked film. However, the inventionprovides such an electrical test methodology by combining VTFL I-Vresult and normal C-V result. The electrical thickness of the individuallayer is thereby easily determined. Furthermore, nitride consumptionrate during re-oxidation is also obtained with the invention. Theactivation energy extracted from temperature dependent SCLC currentshows the characteristics of the traps. Therefore, the SCLC conductionparameters are easily monitored and are used to control the thicknessand the level of defects during DRAM fabrication.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be betterunderstood from the following detailed description of a preferredembodiment(s) of the invention with reference to the drawings, in which:

FIG. 1 illustrates a voltage regulator;

FIG. 2 illustrates two current/voltage curves for two differentthicknesses of the inventive N-O dielectric capacitor;

FIG. 3 illustrates the origin of the conduction mechanism in theinventive N-O films;

FIG. 4 illustrates the conduction parameters dependent on the trappingenergy level, trapping density, nitride thickness and devicetemperature;

FIG. 5 illustrates the VTFL as relatively temperature insensitive asshown by the different temperature curves;

FIG. 6 is a flowchart showing the processing used to make the inventivevoltage regulator;

FIG. 7 is a schematic diagram of a DRAM device according to theinvention;

FIG. 8 is a chart showing the VTFL of a SCLC nitride-oxide capacitorthat is proportional to the square of the film thickness;

FIG. 9 illustrates a planar nitride deposition;

FIG. 10 is a chart illustrating VTFL I-V results; and

FIG. 11 is a chart illustrating C-V results.

DETAILED DESCRIPTION OF THE INVENTION DESCRIPTION OF PREFERREDEMBODIMENTS OF THE INVENTION

The invention presents a simple capacitor structure that has a number ofvery beneficial uses. The N-O capacitor structure described below isformed in a process that intentionally creates defects that thisdisclosure refers to as electron traps. The electron traps produce anumber of benefits including outputting a constant voltage, allowing thethis simple structure to be used as a voltage regulator/voltage sensor.In addition, the level of voltage that is output is directly dependentupon the square of the nitride film thickness. Therefore, the inventivestructure can also be incorporated into capacitor structures, such asdeep trench capacitors, planar capacitors, etc., to allow in-linemonitoring of the nitride film thickness as the various capacitorstructures are being manufactured. As described below, the inventivestructure also includes a number of other useful purposes.

One excellent application for this simple structure is as a voltageregulator because the invention maintains a relative constant voltagedespite minor variations in device current and temperature. Morespecifically, the invention comprises, in one form, a voltage regulatorthat is formed from a nitride-oxide dielectric capacitor. Anotherapplication for this newly-founded characteristic is for better processcontrol of stacked dielectric capacitor fabrication. An importantfeature of the invention is that the nitride-oxide dielectric capacitoris selectively formed to have carrier “traps” that allow the voltageoutput by the inventive voltage regulator to be easily controlled. Adetailed discussion of such traps occurs in “Abrupt Current Increase Dueto Space-Charge-Limited Conduction In Thin Nitride-Oxide StackedDielectric System” by Fen Chen, B. Li, R. Jammy, and R. Dufresne,Journal of Applied Physics, v90, 1898 (2001), incorporated herein byreference.

Traps are formed due to certain amounts of structural disorders such asdefects, dislocations, dangling bonds, impurities, and interface statesinside the nitride film. Those electrically active traps can capture andstore mobile electrons or holes and, thus, affect the carrier density.The traps will greatly reduce the current since initially empty trapswill capture and thereby immobilize most of the injected electrons. Asthe injection level (applied voltage) is raised, all of the traps willeventually become filled and the current will rise sharply back to thetrap-free value. Traps inside the nitride film are strongly dependent onthe film deposition process and post-annealing. By changing depositiontemperature, doping, annealing temperature, and ambient, etc., trapdensity and its energy level can be controlled and modified.

With the inventive device, there is an abrupt current increase at thevoltage VTFL (trap filled limit voltage) before dielectric breakdown.Two things happen when the VTFL is reached. First, the capacitor currentincreases drastically. Secondly, the applied voltage across thecapacitor remains relatively constant over a wide range of devicecurrent values. This allows the invention (in one form) to make anexcellent voltage regulator because it maintains a relatively constantvoltage despite minor variations in capacitor current.

FIG. 1 illustrates one structure in which the invention can be included.As would be known by one ordinarily skilled in the art, the inventivevoltage regulator embodiment could be included in any location where aconventional voltage regulator would appear. In FIG. 1, item 110represents the unfiltered voltage source that produces V_(S). Thisvoltage (V_(S)) can vary depending upon load, temperature, etc. Theinventive voltage regulator is shown as a capacitor D1 (item 116) andregulates (filters) the voltage V_(S) to a value V_(D). Resistor 112represents the resistance between the voltage source 110 and theinventive voltage regulator 116. Therefore, any devices (such asresistor 114) connected to the voltage source 110 and voltage regulator116 would receive a constant voltage supply V_(D). As is also shown inthe voltage-current curve 120 overlaid on the circuit diagram in FIG. 1,over a broad current range, the voltage output by the voltage regulatorremains relatively constant.

As shown in FIG. 2, the inventive device produces an abrupt currentincrease under negative gate polarity. More specifically, FIG. 2illustrates two current/voltage curves for two different thicknesses ofthe inventive N-O device (4.14 nm and 4.49 nm). Current rises nearlyvertically at the voltage VTFL and the VTFL can easily be adjusted byaltering the film thickness as shown in FIG. 2. The inventive device hasthe ability to reproduce the same, nearly vertical, rise at VTFL duringrepeated I-V (current voltage) ramps (cycles). The action of theinventive voltage regulator is not due to dielectric breakdown sinceleakage current is virtually unchanged during each successive I-V ramp.Light emission and C-V measurements further confirm that this sharpcurrent increase is not due to dielectric breakdown.

The properties of SCLC (space-charge-limited conduction) in the N-Oinsulator, having electron traps, indicates that most of theobservations could be qualitatively accounted for. The origin of theconduction mechanism in the inventive N-O films is shown in the banddiagrams of FIG. 3. For the negative gate bias, when the applied voltageis high, the injected electrons tunnel directly from the polysilicon304, through the thin oxide layer 300 and enters the silicon nitrideconduction band 302. This forms space-charges A, B, C that are similarto a vacuum diode.

In a perfect trap-free insulator, all of the injected carriers remainfree and all contribute to the current. However, with the invention,carrier traps are generally formed in the nitride film or at thenitride-oxide interface as a result of a certain amount of structuraldisorders modulated by process. The presence of initial empty trapssignificantly reduces the current by capturing most of the injectedcarriers. As the injection level is raised, all of the traps willeventually become filled and the current will rise sharply back to thetrap-free value. Therefore, in addition to controlling the voltageoutput level by altering the thickness of the N-O dielectric film, theinvention can also control voltage output levels by changing thecharacteristics of the traps.

Details of SCLC conduction parameters depend on the trapping energylevel, trapping density, nitride thickness, and device temperature. Thetrapping level and density could be modulated by different manufacturingprocesses. The invention can intentionally introduce more trappinglevels into the nitride film to have multiple current jumps beforedevice breakdown, as shown in the curve in FIG. 4. Therefore, theinvention, in another embodiment, comprises a multi-value voltageregulator that is made of a single capacitor. In single-crystalmaterial, a single level of traps usually form. However, in general, inamorphous or polycrystalline films, traps are formed at different energylevels, depending upon the nature of short-range order of geometry. Thedifferent environments for different traps possibly results in multiplediscrete trap levels. By modulating the process parameters, multipleenergy level traps can be formed. If two trap levels (one with highenergy level and one with low energy level) co-exist inside the nitridefilm, they both will capture electrons initially to greatly reduce thecurrent. As the applied voltage is raised, the lower energy level trapswill first be filled and the current will rise to a certain high level,but not to the trap-free level. As the applied voltage is raisedcontinuously, the high energy level traps will eventually also be filledand then the current will rise again to trap-free value. As a result,there will be two current sharp jumps for two different VTFL values.

Furthermore, the VTFL is relatively temperature insensitive (dV<0.15Vfrom 30Â° C. to 140Â° C.) as shown by the different temperature curvesin FIG. 5. Therefore, the inventive structure is very stable underdifferent temperature environments as opposed to a regular Zener diodewhich is temperature sensitive.

In addition, both planar and deep trench capacitor N-O films can befabricated with a standard MOS process. As shown in FIGS. 6 and 7, usingwell-known processes, the deep trench 70 is etched (step 60) and the n+type buried plate 71 (bottom contact) is formed (step 61) by, forexample, one of the following methods: gas phase doping, glassout-diffusion, and ion implantation utilizing an N-type dopant such asarsenic or phosphorus. Next, the sidewalls are precleaned using, forexample a typical Huang A and B cleaning with a DHF step in between.

The following steps are performed insitu without break vacuum. First, instep 62 a H2 prebake is performed at 950Â° C. for 30 minutes or less toremove native oxide (this is optional). Then, in item 63 a NH3 bakeprocess at 800Â° C. to 1000Â° C. is performed to grow a thin thermalnitride 72 as a nucleation layer (having a thickness of from about 20 to25A) on the n+ buried plate. Next, in item 64 an LPCVD deposition of SiN73 is made using, for example, dichlorosilance and NH3 as reactant gasesto get the rest of the nitride thickness at 600Â° C.-750Â° C. The totalnitride thickness is preferably in the range of 3-5 nm.

Re-oxidation of the node nitride 73 is performed at about 900Â° C. tooxidize the top nitride to form a thin top oxide layer (so calledre-oxide) 74 of a typical thickness from about 1 to about 2 nm (item65). Next, a heavily n+ doped amorphous/poly-Si 75 is deposited into thedeep trench to form a top contact (item 66). As discussed above, theVTFL of the nitride-oxide capacitor 73, 74 is proportional to the squareof the nitride film thickness due to traps generated inside nitridelayer. Therefore, by observing the VTFL of such a deep trench capacitor,the thickness of the nitride film may easily be determined. As shown inFIG. 8, the VTFL of such a SCLC nitride-oxide capacitor 73, 74 isproportional to the square of the film thickness.

Similarly, for the planar NO capacitor (not shown), the process startsby forming an n+ type buried plate on a Si substrate using well-knowndoping techniques such as gas phase doping, glass out-diffusion, ionimplantation, etc., to form a contact. Prior to forming the nitridelayer on the n+ Si buried plate, the Si substrate may be precleanedusing a Huang-type precleaning process.

Again, the following steps are performed insitu without break vacuum.First, a H2 prebake is performed at 950Â° C. for 30 minutes or less toremove native oxide (this is optional). Then, a NH3 bake process at800Â° C. to 1000Â° C. is performed to grow a thin thermal nitride as anucleation layer (having a thickness of from about 20 to 25A) on the n+buried plate. Next, an LPCVD deposition of SiN is made using, forexample, dichlorosilance and NH3 as reactant gases to get the rest ofthe nitride thickness at approximately 600Â° C.-750Â° C.

Re-oxidation of the node nitride is performed at about 900Â° C. tooxidize the top nitride to form a thin top oxide layer of a typicalthickness from about 1 to 2 nm. Then, a layer of n+ polysilicon isformed on the reoxidized nitride layer to form another contact. The n+layer may be formed by deposition and ion implantation. The typicalthickness is about 3000A.

For example, FIG. 9 illustrates a planar nitride deposition 90 which,through a conventional CV process, produces a first thickness valuet_(n1). After the formation of the re-oxide 91, the VTFL of thestructure indicates the thickness of the nitride film 90 after there-oxidation process t_(n2). In addition, the conventional CV processagain provides a total thickness of both films (nitride and re-oxidationfilms) t_(eff). The total thickness is equal tot_(eff)=t_(ox)+t_(n2)*Î¾_(SiO2)/Î¾_(Si3N4). This process also allows therate of nitride consumption to be determined by subtracting the secondnitride thickness from the original nitride thickness.

By-checking the VTFL across the wafer, the uniformity (thickness anddefect level) of the film (process) can be determined. Therefore, theinvention presents another in-line monitoring function. As shown in FIG.10, the VTFL I-V result is in excellent agreement with the C-V results(shown in FIG. 11). Specifically, the X and Y coordinates in FIGS. 10and 11 are those of the structure itself. In FIG. 10, the Z coordinaterepresents the thickness as determined by the VTFL measurement, whilethe Z coordinate in FIG. 11 represents the thickness as determined bythe conventional CV measurement. Thus, as shown, the invention producesresults that are consistent with conventional in-line monitoringtechniques. However, with the invention, the measurement process (I-V)is substantially simplified comparing with C-V and, therefore, is lessexpensive and less time consuming.

The foregoing manufacturing steps are only exemplary and the inventionis not strictly limited to these processes. To the contrary, as would beknown by one ordinarily skilled in the art, in view of this disclosure,there are a wide variety of processes that could be utilized to form theinventive structure. This invention is easily extended to other stackcapacitor dielectrics and provides broad applications for both memorynode and logic gate processes.

For process control and in-line monitoring application, by using theunique SCLC conduction properties, nitride thickness and the trapsproperties are easily identified and, therefore, better process controlis achieved. Details of SCLC conduction parameters depend on thethickness and temperature. Since the experiments to verify the inventionintentionally keep the reox 300 thickness the same for all of the films,the VTFL depends on nitride 302 thickness only. To detect nitridethickness and reoxide thickness separately for N-O film, the inventioncombines VFTL I-V results and normal C-V results. Furthermore, thenitride consumption rate during reoxidation is also used to determinenitride and reoxide thickness. From the activation energy extracted fromtemperature dependent SCLC current (FIG. 2), it is known that thecharacter and magnitude of space-charge-limit effect are determinedlargely by the presence of the single set of shallow traps. Therefore,from the displacement 2, the energetic location inside the nitrideforbidden gap of those traps could be determined. As a summary, both thevalue of VTFL and current displacement at VTFL can be monitored and usedto control the thickness and the level of defects in N-O insulator.Thus, the above SCLC I-V analysis gives a fast, easy, and direct way tocontrol the N-O thin film fabrication.

The invention has many applications/uses. For a voltage sensorapplication, as current increase occurs only at a very narrow voltageregion, a small voltage shift will dismiss a sharp current jump. Thus,with the inventive device, by monitoring dI/dV, the voltage shifts areaccurately determined. For a SCLC memory device, as the current sharplyincrease at VTFL, two states—before and after current jump with low andhigh current levels are obvious. Therefore, those two current states canbe used as binary on and off states for memory application.

For voltage regulation application, as mentioned above, either a simpleZener diode or complicated IC voltage regulator is conventionally usedin power supply systems. The invention is advantageous over suchstructures because the inventive N-O dielectric device providesmulti-value voltage regulation with a single device, has high thermalstability, provides a wider current range (about 10× wider than a normalZener diode), has a smaller voltage swing (dV<0.0IV), achieves highdevice density (deep-trench approach), and is very simple and low-cost.In addition, the invention provides a combination Decap (filter forreduction of AC ripple voltage) and voltage regulator in a singledevice. Filters are used to reduce the variations in the rectifieroutput signal. In order to produce a constant DC output voltage, it isnecessary to remove as much of the rectifier output variation aspossible. The capacitor filter is the most basic filter type and themost commonly used. The decoupling capacitive filter is simply acapacitor (or capacitor arrays) connected in parallel with the loadresistance. The filtering action is based on the charge/discharge actionof the capacitor. Since the invention's NO voltage regulator is acapacitor, the charge/discharge action can be combined with the voltageregulation application. All of those features provided by NO capacitorsare easily integrated and manufactured using current CMOS processes.

While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims. For example, the invention is easily applied as avoltage sensor or SCLC memory device.

What is claimed is:
 1. A two terminal device comprising: a nucleationlayer; a nitride layer on said nucleation layer; a re-oxide layer onsaid nitride layer; and a conductor on said re-oxide layer; wherein saidnitride layer includes electron traps.
 2. The device in claim 1, whereincharacteristics of said electron traps control a voltage output of saiddevice.
 3. The device in claim 1, wherein a thickness of said nitridelayer and said re-oxide layer control a voltage output of said device.4. The device in claim 1, wherein said nitride layer and said re-oxidelayer comprise one of a voltage regulator, voltage sensor, and memorydevice.
 5. The device in claim 1, wherein said capacitor undergoes atrap filled limit voltage, such that a constant voltage is output for aplurality of currents.
 6. The device in claim 5, wherein trap filledlimit voltage events occur at different voltage levels, such that saiddevice comprises a multi value voltage regulator.
 7. A capacitor voltageregulator device comprising: a nucleation layer; a nitride layer on saidnucleation layer; a re-oxide layer on said nitride layer; and aconductor on said re-oxide layer; wherein said nitride layer includeselectron traps, and wherein a thickness of said nitride layer controls avoltage output of said structure.
 8. The device in claim 7, wherein athickness said re-oxide layer controls a voltage output of said device.9. The device in claim 7, wherein said capacitor undergoes a trap filledlimit voltage, such that a constant voltage is output for a plurality ofcurrents.
 10. The device in claim 9, wherein trap filled limit voltageevents occur at different voltage levels, such that said devicecomprises a multi value voltage regulator.
 11. A method of manufacturinga capacitor structure, said method comprising: thermally growing anucleation layer on a substrate; performing a low pressure chemicalvapor deposition (LPCVD) of silicon nitride on said nucleation layer;re-oxidizing a top portion of said silicon nitride to form a re-oxidelayer; and forming a conductor on said re-oxide layer, wherein saidnitride layer includes electron traps.
 12. The method in claim 11,wherein characteristics of said carrier traps control a voltage outputof said device.
 13. The method in claim 11, wherein a thickness of saidnitride layer and said re-oxide layer modulate a voltage output of saiddevice.
 14. The method in claim 11, wherein said nitride layer and saidre-oxide layer comprise one of a voltage regulator, voltage sensor, andmemory device.
 15. The method in claim 11, wherein said capacitorundergoes a trap filled limit voltage, such that a constant voltage isoutput for a plurality of currents.
 16. The method in claim 15, whereintrap filled limit voltage events occur at different voltage levels, suchthat said capacitor device comprises a multi value voltage regulator.